This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-316349, filed Oct. 30, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and in particular to the technique of forming a gate electrode in a semiconductor device having an n-type MIS transistor and a p-type MIS transistor.
2. Description of the Related Art In recent years, a greater demand has been made for a high-speed, high integration density semiconductor device. In order to realize such a demand, studies have been made on not only the reduction of the element dimension and element-to-element interval dimension but also the achieving of electrodes and wirings of lower resistance. In order to achieve such lower resistance, a policide structure has been widely used in which a metal silicide is stacked on a polycrystalline silicon. With the microminaturization of the semiconductor devices it has been necessary to secure a unit of a still lower resistance.
Under such a situation, a metal gate electrode structure now provides a promising candidate in which a metal film is directly formed on a gate insulating film. In such metal gate electrode structure, however, a new problem arises upon comparison with the polycide structure, etc., in which a polycrystalline silicon is set in contact with the gate insulating film. In the polycide structure, etc., the threshold voltage of a transistor is determined depending upon the impurity concentration of a channel region and the concentration of an impurity in the polycrystalline silicon. In contrast, in the metal gate electrode structure, the threshold voltage of the transistor is determined depending upon the impurity concentration of the channel region and work function of the metal gate electrode. It is, therefore, necessary to adopt a so-called dual metal gate electrode structure using two kinds of gate electrode materials of different work functions for n-type MIS transistor and p-type MIS transistor.
In the dual metal gate electrode structure, it is necessary to use, for the gate electrode of the n-type MIS transistor, a material having a work function xcfx86m of not higher than 4.6 eV or desirably not higher than 4.3 eV. As the material of such a lower work function, Ta and Nb are known. Since Ta and Nb reveal a high reaction with an underlying insulating film, it is difficult to use Ta and Nb as the gate electrode material. Further, a tungsten silicide (WSix) reveals an excellent thermal stability but the work function xcfx86m is of the order of 4.4 eV and it is hardly said that this material is optimal as the gate electrode material of the n-type MIS transistor.
As the prior art, Jpn. Pat. Appln. KOKAI Publication Nos. 8-130216, 8-153804 and 9-246206 disclose the techniques of implanting an impurity ion into a tungsten silicide (WSix) film from the viewpoint of controlling the work function of the gate electrode. Further, Jpn. Pat. Appln. KOKAI Publication No. 10-125919 discloses the technique of implanting an impurity ion into a tungsten silicide film followed by an annealing process.
In these Publications, however, the techniques comprise implanting an impurity ion into the tungsten silicide and problems arise, such as the lowering of a reliability of the gate insulating film, etc., resulting from a damage caused by the ion implantation as well as the difficulty encountered in controlling an impurity concentration distribution in the gate electrode.
As described above, from the standpoint of achieving an electrode and wiring of lower resistance a metal gate electrode structure is proposed. And from the standpoint of controlling the work function of the gate electrode a proposal is made to implant an impurity into the metal silicide film. In the prior art technique, however, since an impurity ion is implanted, the reliability is lowered due to a damage caused by the ion implanation and it is difficult to control the impurity concentration distribution. It is, therefore, difficult to optimize the work function of the gate electrode and to obtain a semiconductor device excellent in its characteristics and its reliability.
According to an aspect of the invention, there is provided a method for manufacturing a semiconductor device having an n-type MIS transistor and a p-type MIS transistor, comprising: forming a first gate insulating film in a first area where the n-type MIS transistor is to be formed; depositing a first conductive film on the first gate insulating film in the first area, the first conductive film containing silicon, a metal element selected from tungsten and molybdenum and an impurity element selected from phosphorus and arsenic; forming a second gate insulating film in a second area where the p-type MIS transistor is to be formed; and forming a second conductive film on the second gate insulating film in the second area, the second conductive film having a work function higher than that of the first conductive film.